Method and circuit for controlled gain reduction of a differential pair
The present document relates to multi-stage amplifiers, such as linear regulators or linear voltage regulators (e.g. low-dropout regulators) configured to provide a constant output voltage subject to load transients. A multi-stage amplifier (100, 200) is described. The multi-stage amplifier (100, 20...
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Main Author | |
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Format | Patent |
Language | English French German |
Published |
14.01.2015
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Subjects | |
Online Access | Get full text |
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Summary: | The present document relates to multi-stage amplifiers, such as linear regulators or linear voltage regulators (e.g. low-dropout regulators) configured to provide a constant output voltage subject to load transients. A multi-stage amplifier (100, 200) is described. The multi-stage amplifier (100, 200) comprises a differential amplification stage (101) which comprises a differential transistor pair (251, 250). The differential amplification stage (101) is configured to provide a stage output voltage at a stage output node (255) of the differential transistor pair (251, 250), based on a first input voltage (107) at a first stage input node and a second input voltage (108) at a second stage input node. The differential transistor pair (251, 250) also comprises a reference node (611). The differential amplification stage (101) further comprises an active load (253, 252) comprising a first diode transistor (253) coupled to the reference node (611) and a first mirror transistor (252) coupled to the stage output node (255). Furthermore, the multi-stage amplifier (100, 200) comprises a gain control circuit (600) arranged in parallel to the active load (253, 252). The gain control circuit (600) comprises a second diode transistor (603) coupled to the stage output node (255) and a second mirror transistor (602) coupled to the reference node (611). |
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Bibliography: | Application Number: EP20130176002 |