THREE-LEVEL INVERTER

A three-level inverter is disclosed, including a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a first capacitor, a second capacitor, a first diode, a second diode, an inductor, and a third capacitor, where the first capacitor...

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Bibliographic Details
Main Author CUI, Zhaoxue
Format Patent
LanguageEnglish
French
German
Published 27.06.2018
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Summary:A three-level inverter is disclosed, including a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a first capacitor, a second capacitor, a first diode, a second diode, an inductor, and a third capacitor, where the first capacitor is connected in series with the second capacitor, and the first capacitor and the second capacitor are connected to a fourth node; the first switching transistor, the second switching transistor, the third switching transistor, and the fourth switching transistor are in series connected in sequence between the first capacitor and the second capacitor; the first switching transistor and the second switching transistor are connected to a first node, the second switching transistor and the third switching transistor are connected to a second node, and the third switching transistor and the fourth switching transistor are connected to a third node; an anode of the first diode is connected to the fourth node, a cathode of the first diode is connected to the first node; a cathode of the second diode is connected to the fourth node, an anode of the second diode is connected to the third node; the inductor is connected in series with the third capacitor between the second node and the fourth node, and the inductor and the third capacitor are connected to a fifth node; and a clamp circuit is connected in parallel between both ends of the third capacitor. The embodiments of the present invention are used to fulfill the following objectives: Only external transistors are turned off in current limitation while current stress of switching transistors is controlled.
Bibliography:Application Number: EP20120858688