Erasing a non-volatile memory (NVM) system having error correction code (ECC)

A method of erasing a non-volatile semiconductor memory device (10) comprising determining a number of bit cells that failed (54)) to erase verify during an erase operation. The bit cells are included in a subset of bit cells in an array of bit cells (12). The method further comprises determining wh...

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Bibliographic Details
Main Authors Baker Jr, Frank K, Mu, Fuchen, He, Chen
Format Patent
LanguageEnglish
French
German
Published 15.08.2018
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A method of erasing a non-volatile semiconductor memory device (10) comprising determining a number of bit cells that failed (54)) to erase verify during an erase operation. The bit cells are included in a subset of bit cells in an array of bit cells (12). The method further comprises determining whether an Error Correction Code (ECC) correction has been previously performed (74) for the subset of bit cells. The erase operation is considered successful if the number of bit cells that failed to erase verify after a predetermined number of erase pulses is below a threshold number and the ECC correction has not been performed for the subset of bit cells (76).
Bibliography:Application Number: EP20130161850