Clock recovery circuit for a receiver using a decision-feedback equalizer

A signal equalization method includes receiving by a decision feedback equalizer (DFE) a first signal comprising transmitted data; adjusting by the DFE the first signal to an equalized signal comprising the transmitted data; detecting by a phase-error detector phase errors at a data rate of no more...

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Bibliographic Details
Main Author HIDAKA, YASUO
Format Patent
LanguageEnglish
French
German
Published 06.05.2015
Subjects
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:A signal equalization method includes receiving by a decision feedback equalizer (DFE) a first signal comprising transmitted data; adjusting by the DFE the first signal to an equalized signal comprising the transmitted data; detecting by a phase-error detector phase errors at a data rate of no more than one fourth of a data rate for the transmitted data; generating by the phase-error detector a phase-error level based on the detected phase errors; and recovering, by a clock-recovery circuit for the DFE and the phase-error detector, a clock signal associated with the transmitted data based on the phase error level.
Bibliography:Application Number: EP20120155064