HYBRID SINGLE AND DUAL-CHANNEL DDR INTERFACE SCHEME BY INTERLEAVING ADDRESS/CONTROL SIGNALS DURING DUAL-CHANNEL OPERATION

A memory structure is described. In one embodiment, the memory structure comprises a memory controller configured to receive a clock signal and to be coupled to a plurality of memory modules via a single address/control bus. The memory controller couples to each of the plurality of memory modules vi...

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Bibliographic Details
Main Authors MAO, Jian, DROP, Michael, SANKURATRI, Raghu
Format Patent
LanguageEnglish
French
German
Published 09.05.2018
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A memory structure is described. In one embodiment, the memory structure comprises a memory controller configured to receive a clock signal and to be coupled to a plurality of memory modules via a single address/control bus. The memory controller couples to each of the plurality of memory modules via a separate chip select signal for each memory module. The memory controller issues commands across the address/control bus to the memory modules in an interleaved fashion in accordance with the timing supplied by the clock. During a waiting period after issuance of a command to one memory module, the memory controller can issue commands to a different memory module.
Bibliography:Application Number: EP20100752664