DATA SPACE ARBITER
A digital processor has a default bus master having a highest priority in a default mode, a plurality of secondary bus masters having associated priorities, wherein the plurality of secondary bus masters have a predetermined priority relationship to each other, and a data space arbiter. The data spa...
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Main Authors | , |
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Format | Patent |
Language | English French German |
Published |
30.05.2012
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Subjects | |
Online Access | Get full text |
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