DATA SPACE ARBITER

A digital processor has a default bus master having a highest priority in a default mode, a plurality of secondary bus masters having associated priorities, wherein the plurality of secondary bus masters have a predetermined priority relationship to each other, and a data space arbiter. The data spa...

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Bibliographic Details
Main Authors CATHERWOOD, MICHAEL, I, DESAI, ASHISH
Format Patent
LanguageEnglish
French
German
Published 30.05.2012
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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