DATA SPACE ARBITER

A digital processor has a default bus master having a highest priority in a default mode, a plurality of secondary bus masters having associated priorities, wherein the plurality of secondary bus masters have a predetermined priority relationship to each other, and a data space arbiter. The data spa...

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Bibliographic Details
Main Authors CATHERWOOD, MICHAEL, I, DESAI, ASHISH
Format Patent
LanguageEnglish
French
German
Published 30.05.2012
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A digital processor has a default bus master having a highest priority in a default mode, a plurality of secondary bus masters having associated priorities, wherein the plurality of secondary bus masters have a predetermined priority relationship to each other, and a data space arbiter. The data space arbiter is programmable in a non-default mode to raise a priority of any of the secondary bus masters to have a priority higher than the priority of the default bus master while maintaining the predetermined priority relationship to only those secondary bus masters for which the priority level also has been raised above the priority of the default bus master.
Bibliography:Application Number: EP20100740057