ASYNCHRONOUS CLOCK GATE WITH GLITCH PROTECTION
The device has a delay stage (DEL) connected with an input of a tristate-buffer to decelerate an input signal (BUF IN) for the buffer. A gate stage (GS) has inputs to receive the decelerated input signal and an asynchronous tristate-signal, which indicates that the buffer is switched in a high-resis...
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Main Author | |
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Format | Patent |
Language | English French German |
Published |
15.05.2019
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Subjects | |
Online Access | Get full text |
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