ASYNCHRONOUS CLOCK GATE WITH GLITCH PROTECTION

The device has a delay stage (DEL) connected with an input of a tristate-buffer to decelerate an input signal (BUF IN) for the buffer. A gate stage (GS) has inputs to receive the decelerated input signal and an asynchronous tristate-signal, which indicates that the buffer is switched in a high-resis...

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Bibliographic Details
Main Author KUHN, Ruediger
Format Patent
LanguageEnglish
French
German
Published 15.05.2019
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Summary:The device has a delay stage (DEL) connected with an input of a tristate-buffer to decelerate an input signal (BUF IN) for the buffer. A gate stage (GS) has inputs to receive the decelerated input signal and an asynchronous tristate-signal, which indicates that the buffer is switched in a high-resistive condition. The gate stage is arranged so that a configuration signal (CS1) is set when the tristate-signal is set, and the input signal and the decelerated signal have a logic level, which indicates that the signal change of the input signal does not spread within the delay stage. An independent claim is also included for a method for operating a tristate-buffer.
Bibliography:Application Number: EP20080838266