SCALABLE ELECTRONICS ARCHITECTURE
A multi-stage missile with plural stages adapted to be physically coupled to and decoupled from adjacent stages and a processor disposed on a single stage for controlling each stage thereof. In the illustrative embodiment, the processor includes a field programmable gate array. In the illustrative e...
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Main Authors | , |
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Format | Patent |
Language | English French German |
Published |
03.08.2016
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Subjects | |
Online Access | Get full text |
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