SCALABLE ELECTRONICS ARCHITECTURE

A multi-stage missile with plural stages adapted to be physically coupled to and decoupled from adjacent stages and a processor disposed on a single stage for controlling each stage thereof. In the illustrative embodiment, the processor includes a field programmable gate array. In the illustrative e...

Full description

Saved in:
Bibliographic Details
Main Authors FACCIANO, ANDREW, B, SHIAU, CHIN, C
Format Patent
LanguageEnglish
French
German
Published 03.08.2016
Subjects
AMMUNITION
BLASTING
EXPLOSIVE CHARGES, e.g. FOR BLASTING, FIREWORKS, AMMUNITION
HEATING
LIGHTING
MECHANICAL ENGINEERING
WEAPONS
Online AccessGet full text

Cover

More Information
Summary:A multi-stage missile with plural stages adapted to be physically coupled to and decoupled from adjacent stages and a processor disposed on a single stage for controlling each stage thereof. In the illustrative embodiment, the processor includes a field programmable gate array. In the illustrative embodiment, the processor is disposed on stage 4 of a four-stage missile and performs guidance and navigation functions for each stage and control functions for stages 2, 3 and 4. In a specific embodiment, a serial bus interface is included for coupling the processor to electronic circuitry on each of the stages of the missile. In the best mode, the interface is an IEEE 1394b interface with a physical layer interface and a link layer interface.
Bibliography:Application Number: EP20070861214