METHOD AND SEMICONDUCTOR MEMORY WITH A DEVICE FOR DETECTING ADDRESSING ERRORS

A semiconductor memory and a data processing system having hardware for carrying out a method for the improved internal monitoring of addressing circuits in semiconductor memories or in a data processing system, in which logic levels addressing lines are tapped off, the actually selected address or...

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Bibliographic Details
Main Authors AMJADI, HOUMAN, TRASKOV, ADRIAN, FEY, WOLFGANG, KABULEPA, LUKUSA DIDIER
Format Patent
LanguageEnglish
French
German
Published 06.07.2011
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A semiconductor memory and a data processing system having hardware for carrying out a method for the improved internal monitoring of addressing circuits in semiconductor memories or in a data processing system, in which logic levels addressing lines are tapped off, the actually selected address or subaddress is represented by additional address bit lines, the actually accessed address/subaddress is recovered using the address bit lines, and the actually selected address/subaddress is compared with the applied address/subaddress, obtained from the additional address bit lines, in order to recognize an error in the addressing circuit.
Bibliography:Application Number: EP20070870213