Multilayer passive circuit topology

• Main Authors: JOHNSTON, ERIC C, PATEL, HARDIK, GOYETTE, WILLIAM R, WINTER, FRANK B
• Format: Patent
• Language: English; French; German
• Published: 15.07.2009
• Subjects: BASIC ELECTRIC ELEMENTS; BASIC ELECTRONIC CIRCUITRY; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; INDUCTANCES; MAGNETS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS; PRINTED CIRCUITS; RESONATORS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES; TRANSFORMERS

A multilayer passive circuit topology is disclosed. In one embodiment, a multilayer circuit is provided. The multilayer circuit comprises a multilayer inductor comprising a first set of parallel conductive traces formed on a first layer, a second set of parallel conductive traces formed on a second layer spaced apart from the first layer; and a plurality of vias that connect respective parallel conductive traces from the first and second layer to form inductor windings. The multilayer circuit further comprises a multilayer capacitor connected to an end of the inductor by a coupling via, the capacitor comprising a first conductive plate and a second conductive plate being spaced apart from one another and being formed on different layers.