Chip scale package using large ductile solder balls

A chip scale (8) package comprising in combination: a. an integrated circuit (10) formed upon a semiconductor die, said semiconductor die having a front surface (12) and an opposing rear surface (16), said semiconductor die including a plurality of conductive bond pads (18, 20) formed upon the front...

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Bibliographic Details
Main Authors HOLLACK, HARRY, ELENIUS, PETER
Format Patent
LanguageEnglish
French
German
Published 09.09.2009
Subjects
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
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Summary:A chip scale (8) package comprising in combination: a. an integrated circuit (10) formed upon a semiconductor die, said semiconductor die having a front surface (12) and an opposing rear surface (16), said semiconductor die including a plurality of conductive bond pads (18, 20) formed upon the front surface thereof for making electrical interconnections to said integrated circuit; b. a patterned metal layer (30) formed over the front surface (12) of said semiconductor die, said patterned metal layer providing a plurality of solder bump pads (26) upon the front surface of said semiconductor die, and said patterned metal layer electrically coupling said conductive bond pads to said plurality of solder bump pads; c. a plurality of ductile solder balls (28), each of said ductile solder balls being secured to a corresponding one of said solder bump pads, each of said ductile solder balls having a generally spherical shape and measuring at least 9 mils (.009 inch) in diameter.
Bibliography:Application Number: EP20090002209