METHOD AND APPARATUS FOR TESTING DATA STEERING LOGIC FOR DATA STORAGE HAVING INDEPENDENTLY ADDRESSABLE SUBUNITS
Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to the memory through the write...
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Format | Patent |
Language | English French German |
Published |
16.06.2010
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Abstract | Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to the memory through the write steering logic and reads the test patterns in parallel to test the write steering logic. The BIST controller writes test patterns to the memory in parallel and reads the test patterns through the read steering logic to test the read steering logic. In both cases, a separate comparator dedicated to each bus lane verifies that the subunit data was properly shifted between the data bus lane and memory storage location subunit. The comparators are effectively disabled during normal operations to prevent logic gate switching. |
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AbstractList | Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to the memory through the write steering logic and reads the test patterns in parallel to test the write steering logic. The BIST controller writes test patterns to the memory in parallel and reads the test patterns through the read steering logic to test the read steering logic. In both cases, a separate comparator dedicated to each bus lane verifies that the subunit data was properly shifted between the data bus lane and memory storage location subunit. The comparators are effectively disabled during normal operations to prevent logic gate switching. |
Author | MUMFORD, CLINT WAYNE KRISHNAMURTHY, ANAND PATEL, SANJAY B MAMILETI, LAKSHMIKANT |
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DocumentTitleAlternate | PROCÉDÉ ET APPAREIL DE TEST DE LOGIQUE D'AIGUILLAGE DE DONNÉES POUR STOCKAGE DE DONNÉES COMPRENANT DES SOUS-UNITÉS ADRESSABLES DE MANIÈRE INDÉPENDANTE VERFAHREN UND VORRICHTUNG ZUM PRÜFEN DER DATENLENKLOGIK FÜR DEN DATENSPEICHER MIT UNABHÄNGIG VONEINANDER ADRESSIERBAREN UNTEREINHEITEN |
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Snippet | Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage... |
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SubjectTerms | INFORMATION STORAGE PHYSICS STATIC STORES |
Title | METHOD AND APPARATUS FOR TESTING DATA STEERING LOGIC FOR DATA STORAGE HAVING INDEPENDENTLY ADDRESSABLE SUBUNITS |
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