METHOD AND APPARATUS FOR TESTING DATA STEERING LOGIC FOR DATA STORAGE HAVING INDEPENDENTLY ADDRESSABLE SUBUNITS

Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to the memory through the write...

Full description

Saved in:
Bibliographic Details
Main Authors MUMFORD, CLINT WAYNE, PATEL, SANJAY B, MAMILETI, LAKSHMIKANT, KRISHNAMURTHY, ANAND
Format Patent
LanguageEnglish
French
German
Published 16.06.2010
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online AccessGet full text

Cover

More Information
Summary:Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to the memory through the write steering logic and reads the test patterns in parallel to test the write steering logic. The BIST controller writes test patterns to the memory in parallel and reads the test patterns through the read steering logic to test the read steering logic. In both cases, a separate comparator dedicated to each bus lane verifies that the subunit data was properly shifted between the data bus lane and memory storage location subunit. The comparators are effectively disabled during normal operations to prevent logic gate switching.
Bibliography:Application Number: EP20070757940