Flat panel display
A flat panel display to maintain resistance of lines at the same level to reduce a luminance difference between the lines includes a plurality of electrodes (14) and a plurality of lead lines (36) to respectively connect a plurality of pads (34) to the plurality of electrodes (14). The lead lines (3...
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Main Author | |
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Format | Patent |
Language | English French German |
Published |
01.10.2008
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Subjects | |
Online Access | Get full text |
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Summary: | A flat panel display to maintain resistance of lines at the same level to reduce a luminance difference between the lines includes a plurality of electrodes (14) and a plurality of lead lines (36) to respectively connect a plurality of pads (34) to the plurality of electrodes (14). The lead lines (36) are formed in a parallelogram shape in which resistivity and line thickness are the same for each lead line, and a length L and a line width W of each lead line are selected such that a value obtained by dividing the length L by the line width W satisfies the equation: L 1 W 1 = L 2 W 2 = L 3 W 3 = ¦ ¦ = L n W n , where L1, L2, L3, ..., and Ln respectively refers to long side lengths, which are direct line distances between the electrode (14) and the pad (34), of the respective lead lines (36) formed in the parallelogram shape, and W1, W2, W3, . , and Wn respectively refers to widths, which are short side distances of the respective lead lines (36) formed in the parallelogram shape. |
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Bibliography: | Application Number: EP20070119848 |