A DEVICE HAVING A LOW LATENCY SINGLE PORT MEMORY UNIT AND A METHOD FOR WRITING MULTIPLE DATA SEGMENTS TO A SINGLE PORT MEMORY UNIT
A method and a device. The device includes a single port memory unit that includes multiple memory regions, whereas each memory region is adapted to receive multiple data segments in parallel; whereas the single port memory unit receives a memory clock signal; characterized by including access logic...
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Main Authors | , , |
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Format | Patent |
Language | English French German |
Published |
11.06.2008
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Subjects | |
Online Access | Get full text |
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Summary: | A method and a device. The device includes a single port memory unit that includes multiple memory regions, whereas each memory region is adapted to receive multiple data segments in parallel; whereas the single port memory unit receives a memory clock signal; characterized by including access logic adapted to receive multiple data segment write requests from multiple data sources; to write, during a first memory clock cycle, multiple data segments to a certain memory region in response to an availability of the certain memory region; to temporarily store rejected data segments; to write, during a second memory clock cycle, at least the rejected data segments, to another memory region. |
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Bibliography: | Application Number: EP20050784494 |