ALIGNED LOGIC CELL GRID AND INTERCONNECT ROUTING ARCHITECTURE

A method for defining an aligned logic cell grid and interconnect layout of a semiconductor integrated circuit having a logic cell is disclosed. The interconnect layout is resized in accordance with a highest common denominator of an initial routing pitch of the interconnect layout and a transistor...

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Bibliographic Details
Main Author MORTON, SHANNON VANCE
Format Patent
LanguageEnglish
French
German
Published 05.12.2007
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A method for defining an aligned logic cell grid and interconnect layout of a semiconductor integrated circuit having a logic cell is disclosed. The interconnect layout is resized in accordance with a highest common denominator of an initial routing pitch of the interconnect layout and a transistor pitch of the logic cell. The cell grid is aligned with the resized routing pitch which provides efficient routing density and transistor performance, minimizes excess transistor area and wire routing waste while maximizing cell packing density.
Bibliography:Application Number: EP20060709809