COHERENT CACHING OF LOCAL MEMORY DATA

A multi processor system 1 comprises a plurality of processors 21 to 25, a system bus 30 and a main system memory 40. Each processor 21 to 25 is connected to a respective cache memory 41 to 45, with each cache memory 41 to 45 in turn being connected to the system bus 30. The cache memories 41 to 45...

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Bibliographic Details
Main Author HOOGERBRUGGE, JAN
Format Patent
LanguageEnglish
French
German
Published 05.09.2007
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A multi processor system 1 comprises a plurality of processors 21 to 25, a system bus 30 and a main system memory 40. Each processor 21 to 25 is connected to a respective cache memory 41 to 45, with each cache memory 41 to 45 in turn being connected to the system bus 30. The cache memories 41 to 45 store copies of data or instructions that are used frequently by the respective processors 21 to 25, thereby eliminating the need for the processors 21 to 25 to access the main system memory 40 during each read or write operation. Processor 25 is connected to a local memory 50 having a plurality of data blocks (not shown). According to the invention, the local memory 50 has a first port 51 for connection to its respective processor 25. In addition, the local memory 50 has a second port 52 connected to the system bus 30, thereby allowing one or more of the other processors 21 to 24 to access the local memory 50. The invention enables the coherent caching of local memory data, using local memory devices that are less expensive, faster, and having more predicable timing than cache memories.
Bibliography:Application Number: EP20050802168