INTEGRATED CIRCUIT SELF-TEST ARCHITECTURE

An integrated circuit (1) comprises a monitor (M1, M3, M3) operable to produce monitor data in dependence upon a measured parameter of the integrated circuit (1); and a self test controller (28) connected to receive monitor data from the monitor (M1, M2, M3). The self-test controller is also operabl...

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Bibliographic Details
Main Authors PELGROM, MARCEL, VEENDRICK, HENDRICUS, J., M
Format Patent
LanguageEnglish
French
German
Published 11.02.2009
Subjects
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Summary:An integrated circuit (1) comprises a monitor (M1, M3, M3) operable to produce monitor data in dependence upon a measured parameter of the integrated circuit (1); and a self test controller (28) connected to receive monitor data from the monitor (M1, M2, M3). The self-test controller is also operable to output self test data from the integrated circuit. The monitor includes an output shift register (SR1, SR2, SR3) and is operable to output monitor data through the shift register (SR1, SR2, SR3). Such a system enables simplified communication of system self test results on an integrated circuit.
Bibliography:Application Number: EP20050807208