MOS-GATED TRANSISTOR WITH REDUCED MILLER CAPACITANCE

A trench MOS-gated transistor is formed as follows. A first region of a first conductivity type is provided. A well region of a second conductivity type is then formed in an upper portion of the first region. A trench is formed which extends through the well region and terminates within the first re...

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Bibliographic Details
Main Authors KOCON, CHRISTOPHER, BOGUSLAW, SHENOY, PRAVEEN, MURALEEDHARAN
Format Patent
LanguageEnglish
French
German
Published 24.12.2008
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A trench MOS-gated transistor is formed as follows. A first region of a first conductivity type is provided. A well region of a second conductivity type is then formed in an upper portion of the first region. A trench is formed which extends through the well region and terminates within the first region. Dopants of the second conductivity type are implanted along predefined portions of the bottom of the trench to form regions along the bottom of the trench which are contiguous with the well region such that when the transistor is in an on state the deeper portion of the well region prevents a current from flowing through those channel region portions located directly above the deeper portion of the well region.
Bibliography:Application Number: EP20050802949