AUTOMATIC CLOCK SPEED CONTROL

Clock speed is controlled based upon the supply voltage to a digital device. When the supply voltage is below a reference voltage the clock speed will be slower than if the supply voltage is above the reference voltage. A phase-lock-loop (PLL) may be used to generate a higher frequency that is an in...

Full description

Saved in:
Bibliographic Details
Main Authors OTTEN, DAVID, L, BUTLER, DANIEL, WILLIAM, JULICHER, JOSEPH, HARRY
Format Patent
LanguageEnglish
French
German
Published 16.01.2008
Subjects
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:Clock speed is controlled based upon the supply voltage to a digital device. When the supply voltage is below a reference voltage the clock speed will be slower than if the supply voltage is above the reference voltage. A phase-lock-loop (PLL) may be used to generate a higher frequency that is an integer multiple of a reference oscillator. The clock speed will be proportional to the frequency multiplication of the PLL when the faster clock speed is selected. A multiplexer is used to switch between different frequency sources, and a timer can be used to insure stable operation of the PLL. A status configuration register has status and control bits for indicating and controlling operation of the clock speed control. A universal serial bus (USB) device can operate at a slower clock with reduced operating voltage, and at a faster clock with increased operating voltage.
Bibliography:Application Number: EP20050754513