Inversion bit line, charge trapping non-volatile memory and method of operating same

A charge trapping memory device in which a field induced inversion layer is used to replace the source and drain implants. The memory cells are adapted to store two bits, one on the left side and one on the right side of the charge trapping structure. A positive threshold voltage erase state is indu...

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Bibliographic Details
Main Author LUNG, HSIANG-LAN
Format Patent
LanguageEnglish
French
German
Published 15.09.2010
Subjects
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A charge trapping memory device in which a field induced inversion layer is used to replace the source and drain implants. The memory cells are adapted to store two bits, one on the left side and one on the right side of the charge trapping structure. A positive threshold voltage erase state is induced using negative gate voltage Fowler Nordheim FN tunneling which establishes a charge balanced condition at a positive voltage. A low current, source side, hot electron injection programming method is used.
Bibliography:Application Number: EP20050010867