Self testing and securing RAM system and method

A self-testing and correcting read only memory (RAM) device and methodology is disclosed herein. The device includes at least one array of memory to enable data storage and self-testing RAM interface for evaluating, correcting, and/or compensating for memory cell errors. The RAM device, via the self...

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Bibliographic Details
Main Author CALLAGHAN, DAVID M
Format Patent
LanguageEnglish
French
German
Published 11.07.2012
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A self-testing and correcting read only memory (RAM) device and methodology is disclosed herein. The device includes at least one array of memory to enable data storage and self-testing RAM interface for evaluating, correcting, and/or compensating for memory cell errors. The RAM device, via the self-testing RAM interface, supports interaction with a central processing unit (CPU) to facilitate testing of the CPU to memory interface as well as the device memory array. Furthermore, the subject invention provides for a system and method of securely storing data to volatile memory. More specifically, the RAM interface component can be employed to, among other things, store data in noncontiguous locations, encrypt/decrypt data as well as perform authentication checks to ensure the integrity of data and/or deter attacks thereon. All or significant portions of such functionality can be performed without burdening the CPU and affecting processing speed or efficiency.
Bibliography:Application Number: EP20050019788