A METHOD FOR ACCESSING A BUS IN A CLUSTERED INSTRUCTION LEVEL PARALLELISM PROCESSOR

• Main Authors: VAN ACHT, VICTOR, M., G, TERECHKO, ANDREI, PIRES DOS REIS MOREIRA, ORLANDO, M
• Format: Patent
• Language: English; French; German
• Published: 05.10.2005
• Edition: 7
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The basic idea of the invention is to add switches along a bus, in order divide the bus into smaller independent segments by opening/closing said switches. A clustered Instruction Level Parallelism processor comprises a plurality of clusters (C 1 -C 6 ) each comprising at least one register file (RF) and at least one functional unit (FU), a bus means ( 100 ) for connecting said clusters (C 1 -C 6 ), wherein said bus ( 100 ) comprises a plurality of bus segments ( 100 a , 100 b , 100 c), and switching means ( 200 ), which is arranged between adjacent bus segments ( 100 a , 100 b , 100 c). Said switching means ( 200 ) are used for connecting or disconnecting adjacent bus segments ( 100 a , 100 b , 100 c). Furthermore, a method for accessing a bus ( 100 ) in a clustered Instruction Level Parallelism processor is shown. Said bus ( 100 ) comprises at least one switching means ( 200 ) along said bus ( 100 ). A cluster can either perform a sending operation based on a source register and transfer word or a receiving operation based on a designation source register and a transfer word. Said switching means are then opened/closed according to said transfer word.