Data synchronization arrangement
The data synchronization device uses a buffer memory (12) with a defined limited number of memory locations, associated with a write-in selection multiplexer (10) and a read-out selection multiplexer (14), for write-in and read-out of data to and from the memory locations. The write-in selection mul...
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Main Authors | , |
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Format | Patent |
Language | English French German |
Published |
05.04.2006
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Subjects | |
Online Access | Get full text |
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