Data synchronization arrangement

The data synchronization device uses a buffer memory (12) with a defined limited number of memory locations, associated with a write-in selection multiplexer (10) and a read-out selection multiplexer (14), for write-in and read-out of data to and from the memory locations. The write-in selection mul...

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Bibliographic Details
Main Authors GOLLER, JOERG, REICHEL, NORBERT
Format Patent
LanguageEnglish
French
German
Published 05.04.2006
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:The data synchronization device uses a buffer memory (12) with a defined limited number of memory locations, associated with a write-in selection multiplexer (10) and a read-out selection multiplexer (14), for write-in and read-out of data to and from the memory locations. The write-in selection multiplexer and the read-out selection multiplexer are operated in synchronization with a clock (WR-CLOCK) of a first clock region and a clock (RD-CLOCK) of a second clock region respectively, using a write-in selection shift register (16) and a read-out selection shift register (18).
Bibliography:Application Number: EP20050004796