integrated circuit with multiple functions sharing multiple internal signal buses according to distributed bus access and control arbitration

A microprocessor that executes instructions to process data in accordance with periodic cycles of a microprocessor system clock. A three-stage pipeline has decode (70), execute (72) and writeback (74) stages. The execution unit fetches instructions and operands and computes memory addresses utilized...

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Main Authors HAINES, RALPH WARREN, HERRINGTON, DANIEL R, PANG, JIANHUA, HELEN, O'NEILL, DAN CRAIG, MARLEY, BRIAN J, GUNTHER, JOHN R, WATERSON, KENT B, WEINMAN, DAVID S, SHAY, MICHAEL J, DIVIVIER, ROBERT J, NEMIROVSKY, MARIO, PEREZ, ALEXANDER, PRIES, STEPHEN C, COLGAN, JAMES A
Format Patent
LanguageEnglish
French
German
Published 10.09.2003
Edition7
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A microprocessor that executes instructions to process data in accordance with periodic cycles of a microprocessor system clock. A three-stage pipeline has decode (70), execute (72) and writeback (74) stages. The execution unit fetches instructions and operands and computes memory addresses utilized in retrieving these from storage and in writing results to storage. The decode unit also has a prefetch unit and microsequencer.
Bibliography:Application Number: EP20030007738