METHOD AND STRUCTURE FOR TEMPERATURE STABILIZATION IN SEMICONDUCTOR DEVICES

Method and structure for temperature stabilization in semiconductor devices are disclosed. In one embodiment, a carbon-based polymer is deposited on top of an interconnect metal line in the semiconductor die where relatively large power dissipation is known to occur. Reduction of the range of temper...

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Bibliographic Details
Main Authors HASHEMI, SEYED, H, CHUNGPAIBONNPATANA, SURASIT, LANGARI, ABDOLREZA
Format Patent
LanguageEnglish
French
German
Published 30.07.2014
Subjects
Online AccessGet full text

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Summary:Method and structure for temperature stabilization in semiconductor devices are disclosed. In one embodiment, a carbon-based polymer is deposited on top of an interconnect metal line in the semiconductor die where relatively large power dissipation is known to occur. Reduction of the range of temperature excursions in the semiconductor die is achieved since the polymer acts as a cushion to dampen the range of temperature excursions of the semiconductor die. During occurrence of power pulses in the semiconductor die, the polymer absorbs energy from the interconnect metal, and thus from the semiconductor devices that are connected to the interconnect metal, by expanding without a rise in the temperature of the polymer. The energy generated when power pulses are being dissipated in the semiconductor die does not result in a substantial rise in the temperature of the polymer. Accordingly, the temperature of the semiconductor devices that are connected to the interconnect metal is not abruptly increased during power pulses. Similarly, during the time that no power pulse is being dissipated by the semiconductor die, the polymer releases the stored energy by contracting to its original shape while maintaining a constant temperature. Thus, the temperature of semiconductor devices which are in thermal contact with the polymer is not abruptly decreased when no power pulse is being dissipated in the semiconductor die. In this manner the range of temperature excursions in the semiconductor die is reduced.
Bibliography:Application Number: EP20010971052