Method for exposing at least one or at least two semiconductor wafers

Semiconductor wafers (1, 2), e.g. a lot (10), are exposed after an alignment (20) in a wafer stepper or scanner (35) with each determining their alignment parameters. Using, e.g., a linear formula with tool specific coefficients the overlay accuracy can be calculated from these alignment parameters...

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Bibliographic Details
Main Authors SCHMIDT, SEBASTIAN, OTTO, RALF, SCHEDEL, THORSTEN, FISCHER, THOMAS, HOMMEN, HEIKO
Format Patent
LanguageEnglish
French
German
Published 28.08.2002
Edition7
Subjects
APPARATUS SPECIALLY ADAPTED THEREFOR
BASIC ELECTRIC ELEMENTS
CINEMATOGRAPHY
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
ELECTROGRAPHY
HOLOGRAPHY
MATERIALS THEREFOR
ORIGINALS THEREFOR
PHOTOGRAPHY
PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES
PHYSICS
SEMICONDUCTOR DEVICES
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Summary:Semiconductor wafers (1, 2), e.g. a lot (10), are exposed after an alignment (20) in a wafer stepper or scanner (35) with each determining their alignment parameters. Using, e.g., a linear formula with tool specific coefficients the overlay accuracy can be calculated from these alignment parameters in advance to a high degree of accuracy as if a measurement with an overlay inspection tool (40) had been performed. The exposure tool-offset can be adjusted on a wafer-to-wafer basis to correct for the overlay inaccuracy derived. Moreover, the alignment parameters for a specific wafer can be used to change the tool-offset for the same wafer prior to exposure. The required inspection tool (40) capacity is advantageously reduced, the wafer rework decreases and time is saved to perform the exposure step (30).
Bibliography:Application Number: EP20010104358