A METHOD AND INTEGRATED CIRCUIT ARRANGED FOR FEEDING A TEST FORCING PATTERN ON A SINGLE SHARED PIN OF THE CIRCUIT

An integrated circuit is forced into a test mode through executing the following steps: presenting a test forcing pattern on a subset of the circuit's external pins for driving the circuit to a test mode, presenting the electronic test forcing pattern to the circuit and finally executing the te...

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Bibliographic Details
Main Author MELI, LOUIS, M
Format Patent
LanguageEnglish
French
German
Published 03.08.2005
Edition7
Subjects
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Summary:An integrated circuit is forced into a test mode through executing the following steps: presenting a test forcing pattern on a subset of the circuit's external pins for driving the circuit to a test mode, presenting the electronic test forcing pattern to the circuit and finally executing the test proper. In particular, the following steps are implemented: presenting the pattern on a single pin in the form of an aggregate of a clocking sequence and a transition signalling data sequence as input data for an on-circuit storage element; clocking the storage element by a delayed version of the test forcing pattern; sequentially storing successive data parts of the test forcing pattern under control of successive clock parts of the delayed test forcing pattern; matching a predetermined string of the stored data parts versus a standard pattern, and upon finding a match driving the circuit to a test condition for then executing a test procedure.
Bibliography:Application Number: EP20000979546