Testing simulated chips

• Main Authors: JUE, DARREN S, GUPTA, ASHISH
• Format: Patent
• Language: English; French; German
• Published: 31.10.2001
• Edition: 7
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; MEASURING; MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES; PHYSICS; TESTING

Verification of the functional design of the response of a system (10) to propagation delays from the inputs of source synchronous links during testing is performed by a system which emulates propagation delays by receiving a data slice or data slices (18) from a source (12), applying a random or known delay to the data slice (12), and sending the delayed data slice (12) to the chip (16) under test. Data slices (18) having varying delay values may be used to test combinations of delays. A programmable delay element (14) is used to emulate the propagation delays. This may be implemented at the hardware description level by receiving the data slice (18) onto multiple data buses (24), applying a different delay to the data slice (18) on each data bus (24), and sending the delayed data slices (18) as inputs into a multiplexor (20). The multiplexor (20) may have a selector input (22) that determines which amount of delay to test. Alternatively, the delay may be emulated using a higher level programming language and creating a multidimensional array (30). In one dimension, the array (30) receives different data slices (18), and in the other it assigns different delay values (32). The multidimensional array (30) then receives multiple data slices (18) at the same time. Each delay value (32) is stored in a different array (30) location, depending upon the delay (32) assigned to the data slice (18). An output entry (34) is sent to the chip (16) under test. The array (30) entries may be shifted each clock cycle to the output entry (34), or a pointer (36) may be used to specify a different output entry (34) each clock cycle.