Process for manufacturing electronic devices comprising high-voltage MOS and EEPROM transistors

• Main Authors: VAJANA, BRUNO, PATELMO, MATTEO
• Format: Patent
• Language: English; French; German
• Published: 26.05.2010
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

For manufacturing an HV MOS transistor (80) having a low multiplication coefficient and a high threshold, a non-implanted area (6) of the substrate is used. This area thus has the same conductivity type and the same doping level as the substrate. The transistor is obtained by forming, over the non-implanted substrate area, a first gate region (43a) of semiconductor material having the same doping type as the non-implanted substrate area; and forming, inside the non-implanted substrate area, first source and drain regions (64a) of a second conductivity type, arranged at the sides of the first gate region (43a). At the same time, also a dual-gate HV MOS transistor (81) is formed, the source and drain regions (64b) of which are housed in a tub (13) formed in the substrate (2) and having the first conductivity type, but a higher concentration than the non-implanted substrate area. It is moreover possible to form a nonvolatile memory cell (82) simultaneously in a second tub (14) of the substrate (2) of semiconductor material.