Mixed signal silicon MOS integrated circuit

The specification describes MOS transistors for analog functions which have increased output impedance. The increased output impedance is the result of reduced drain depletion width. This is accomplished without adverse effects on other device parameters. The MOS transistor structures have an implan...

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Bibliographic Details
Main Authors TARSIA, MAURICE, ESHRAGHI, ALI, GOPINATHAN, VENUGOPAL, KHOURY, JOHN MICHAEL, VUONG, THI-HONG-HA
Format Patent
LanguageEnglish
French
German
Published 19.07.2000
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:The specification describes MOS transistors for analog functions which have increased output impedance. The increased output impedance is the result of reduced drain depletion width. This is accomplished without adverse effects on other device parameters. The MOS transistor structures have an implant added to the lightly doped drain (LDD) with a conductivity type opposite to that of the LDD and a doping level higher than the channel doping. The added implant confines the spread of the depletion layer and reduces its width. A relatively small confinement results in a significant increase in output impedance of the device, and a corresponding increase in transistor gain.
Bibliography:Application Number: EP19990310127