Process for integrating in a same chip a non-volatile memory and a high-performance logic circuitry

• Main Authors: MAURELLI, ALFONSO, CAPPELLETTI, PAOLO GIUSEPPE
• Format: Patent
• Language: English; French; German
• Published: 26.12.2012
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A process for the manufacturing of an integrated circuit including a low operating voltage, high-performance logic circuitry and an embedded memory device having a high operating voltage higher than the low operating voltage of the logic circuitry, providing for: on first portions of a semiconductor substrate (1), forming a first gate oxide layer (3) for first transistors operating at the high operating voltage; on second portions of the semiconductor substrate (1), forming a second gate oxide layer (5) for memory cells of the memory device; on the first and second gate oxide layers (3,5), forming from a first polysilicon layer (6) gate electrodes (8,9) for the first transistors, and floating-gate electrodes (7) for the memory cells; forming over the floating-gate electrodes (7) of the memory cells a dielectric layer (18); on third portions of the semiconductor substrate (1), forming a third gate oxide layer (24) for second transistors operating at the low operating voltage; on the dielectric layer (18) and on the third portions of the semiconductor substrate (1), forming from a second polysilicon layer (25) control gate electrodes (29) for the memory cells, and gate electrodes (26,27) for the second transistors; in the first portions of the semiconductor substrate (1), forming source and drain regions (12,13;16,17) for the first transistors; in the second portions of the semiconductor substrate (1), forming source and drain regions (30,31) for the memory cells; in the third portions of the semiconductor substrate (1), forming source and drain regions for the second transistors.