Electronic device comprising EEPROM memory cells, HV transistors, and LV transistors with silicided junctions, as well as manufacturing method thereof

• Main Authors: VAJANA, BRUNO, DALLA LIBERA, GIOVANNA, GALBIATI, NADIA, PATELMO, MATTEO
• Format: Patent
• Language: English; French; German
• Published: 19.05.2010
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A method for manufacturing electronic devices, comprising memory cells (72) and LV transistors (70) with salicided junctions, comprising, in sequence, the steps of: depositing an upper layer (43) of polycrystalline silicon; defining the upper layer, obtaining floating gate regions (43b) on first areas, LV gate regions (43a) on second areas (13) of a substrate (2), and undefined regions (43) on the first and third areas of the substrate; forming first cell source regions (49 and 50) laterally to the floating gate regions (43b); forming LV source and drain regions (55) laterally to the LV gate regions; forming a silicide layer (57a1, 57a2, 57) on the LV source and drain regions (55), on the LV gate regions (43a), and on the undefined portions (43); defining HV gate regions (43d) on the third areas, and selection gate regions (43c) on the first areas (14); forming source regions (65a) laterally to the selection gate regions (43c), and source and drain regions (64) laterally to the HV gate regions.