AN INTEGRATED CIRCUIT WHICH USES A RECESSED LOCAL CONDUCTOR FOR PRODUCING STAGGERED INTERCONNECT LINES

An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar...

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Bibliographic Details
Main Authors HAUSE, FRED, N, DAWSON, ROBERT, BRENNAN, WILLIAM, S, BANDYOPADHYAY, BASAB, MICHAEL, MARK, W, FULFORD, H., JIM, JR
Format Patent
LanguageEnglish
French
German
Published 26.10.2005
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.
Bibliography:Application Number: EP19970907668