A structure of and method for forming a mis field effect transistor

• Main Authors: OKUNO, YASUTOSHI, SUMMERFELT, SCOTT R
• Format: Patent
• Language: English; French; German
• Published: 30.06.1999
• Edition: 6
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A structure for, and method of forming, a metal-insulator-semiconductor field-effect transistor in an integrated circuit. The method comprises forming a germanium layer 52 on a semiconductor substrate (e.g. silicon 20), depositing a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) on the germanium layer, and forming a gate electrode (e.g., titanium nitride 60) on the gate dielectric. The method may comprise forming source and drain regions 64 in the substrate on either side of the gate dielectric. The germanium layer, which is preferably epitaxially grown, generally prevents formation of a low dielectric constant layer between the gate dielectric and the semiconductor substrate. The disclosed structure comprises a germanium layer 52 disposed on a semiconductor substrate (e.g. silicon 20), a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) disposed on the germanium layer, and a gate electrode (e.g., titanium nitride 60) disposed on the gate dielectric. The structure may comprise source and drain regions 64 disposed in the substrate on either side of the gate dielectric. A GexSi1-x buffer layer may be formed between the semiconductor substrate and the germanium layer, with x transitioning from about 0 near the substrate to about 1 near the germanium layer. The large-permittivity gate dielectric may be either a moderate-dielectric constant oxide or a high-dielectric constant oxide.