Circuit and method to externally adjust internal circuit timing

The method involves providing two signal paths. A test mode signal determines a mode of operation. The integrated circuit device is in the first mode of operation when the test mode signal is at a first signal level and in the second mode of operation when the test mode signal is at a second signal...

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Bibliographic Details
Main Authors WONG, HING, KIRIHATA, TOSHIAKI, KRSNIK, BOZIDAR
Format Patent
LanguageEnglish
French
German
Published 04.11.1998
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
STATIC STORES
TESTING
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Summary:The method involves providing two signal paths. A test mode signal determines a mode of operation. The integrated circuit device is in the first mode of operation when the test mode signal is at a first signal level and in the second mode of operation when the test mode signal is at a second signal level. When the integrated circuit device is in the first mode of operation, the first signal path receives an internal signal and generates a first output signal in response to the internal signal. The first output signal is used to derive the timing of the internal control signal in the first mode of operation. When the integrated circuit device is in the second mode of operation, the second signal path receives an external signal provided at an external pin of the integrated circuit and generates a second output signal in response to the external signal. The second output signal is used to derive the timing of the internal control signal in the second mode of operation.
Bibliography:Application Number: EP19970310403