Method of synchronizing a pair of central processor units for duplex, lock-step operation

A method of synchronizing a pair of substantially identical processors for substantial lock-step operation is disclosed. One of the processors is operational, executing an instruction stream from a memory element exclusive to that processor; the other processor is in a wait state. The method involve...

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Main Authors WATSON, WILLIAM JOEL, BAKER, WILLIAM EDWARD, BUNTON, WILLIAM PATTERSON, FOWLER, DANIEL L, SONNIER, DAVID PAUL, KRAUSE, JOHN C, JONES, CURTIS WILLARD, JR, SIMPSON, MICHAEL P
Format Patent
LanguageEnglish
French
German
Published 11.12.1996
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:A method of synchronizing a pair of substantially identical processors for substantial lock-step operation is disclosed. One of the processors is operational, executing an instruction stream from a memory element exclusive to that processor; the other processor is in a wait state. The method involves copying the instruction and data content of the memory of the operating processor to the memory of the waiting processor in a manner that stores the transferred instructions and data in the memory of the waiting processor at locations that correspond to where the instructions and data are located in the memory of the operating processor. Thereafter, the operating processor will periodically send selected ones of the instructions and data to the waiting processor.
Bibliography:Application Number: EP19960304176