Duplicate cache tag memory system

An improved memory system for a shared memory multiprocessor computer system in which one or more processor modules and/or input/output modules have cache memories (50, 52, 54). The main memory controller (14, 16) for each main memory (15, 17) of the system maintains a duplicate cache tag array (44,...

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Bibliographic Details
Main Authors HASSOUN, JOSEPH H, ODINEAL, ROBERT D, ZIEGLER, MICHAEL L
Format Patent
LanguageEnglish
French
German
Published 08.11.1995
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:An improved memory system for a shared memory multiprocessor computer system in which one or more processor modules and/or input/output modules have cache memories (50, 52, 54). The main memory controller (14, 16) for each main memory (15, 17) of the system maintains a duplicate cache tag array (44, 46) containing current information on the status of data lines from that main memory that are stored in the cache memories (50, 52, 54). Thus, coherency checks can be performed directly by the main memory controller (14, 16). This eliminates the need for each processor having a cache memory to perform a separate coherency check and to communicate the results of its coherency checks to the main memory controller, and thereby reduces delays associated with processing coherent transactions.
Bibliography:Application Number: EP19950101636