DRAM cell structure with capacitor over bit line and method of making the same

• Main Author: TEMMLER, DIETMAR
• Format: Patent
• Language: English; French; German
• Published: 29.05.2002
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The invention relates to a one-transistor storage cell arrangement for very highly integrated dynamic semiconductor memory chips in accordance with the stacked-capacitor principle (STC), and a method for producing them (division of EP 0 443 439 A2). The invention is based on the object of eliminating the guard band between bit line and drain contact window via which the STC storage electrode is connected to the MOS selection transistor and which has previously been necessary due to adjustment in accordance with the prior art in STC storage cells with the STC storage capacity complex arranged above the bit line plane (COB structure), independently of the actual structure of the generally three dimensional STC storage capacitor. This is intended to reduce the storage cell layout area, to be able to implement a rectangular intersection of word and bit line run which is advantageous with respect to the performance of the selection transistor and to make the adjustment process of the drain contact window plane with respect to the bit line plane insensitive to tolerance so that memory chips with higher performance and more densely packed can be produced with higher technological reliability and yield. According to the invention, this object is achieved by the fact that an insulated conducting rectangle which is in contact with the drain region penetrates through the insulation layers below and above the bit line and the bit line itself and changes into the underside of the STC memory electrode, is arranged as conducting connection between drain of the MOS selection transistor and STC storage electrode of any design, this rectangle being covered in a self-aligning manner at its circumference by an insulation jacket with constant thickness which ensures the lateral insulation to the intersected bit line leading around the rectangle on one or both sides.