Method of opening windows in dielectric layers of an integrated circuit

• Main Authors: NKANSAH, FRANKLIN DANIEL, ALUGBIN, DAYO, OLASUPO, KOLAWOLE RAHMAN
• Format: Patent
• Language: English; French; German
• Published: 18.05.1994
• Edition: 5
• Subjects: BASIC ELECTRIC ELEMENTS; CHEMICAL SURFACE TREATMENT; CHEMISTRY; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY IONIMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; COATING MATERIAL WITH METALLIC MATERIAL; COATING METALLIC MATERIAL; DIFFUSION TREATMENT OF METALLIC MATERIAL; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL; METALLURGY; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLICMATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASSC23 AND AT LEAST ONEPROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25; NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; SEMICONDUCTOR DEVICES; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THESURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION

A method for forming an integrated circuit with a planarized dielectric (e.g., 43) is disclosed. Runners (e.g., 25) and gates (e.g., 23) are covered with a protective dielectric layer (e.g., 21). Then a conventional dielectric (e.g., 43) is deposited and planarized over the entire circuit surface. When windows (e.g., 49, 47) are opened to runners and to source (e.g.,27)/drain (e.g., 29) regions, the protective dielectric (e.g., 21) helps to slow the etch process over the runner (e.g., 25), thus protecting the runner (e.g., 25) from damage during the extra time required for the etch process to reach the source (e.g., 27) or drain (e.g., 29).