Single-transistor electrically programmable integrated memory

The invention relates to a novel electrically programmable and erasable memory cell. The cell includes a single transistor which is a floating-gate transistor, with no selection transistor. Means are provided for establishing considerable capacitive coupling between the drain (12) and the floating g...

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Bibliographic Details
Main Author DEVIN, JEAN
Format Patent
LanguageEnglish
French
German
Published 19.10.1994
Edition5
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:The invention relates to a novel electrically programmable and erasable memory cell. The cell includes a single transistor which is a floating-gate transistor, with no selection transistor. Means are provided for establishing considerable capacitive coupling between the drain (12) and the floating gate (18). The capacitive coupling between the source (10) and the floating gate is weak as is customary. Preferably, the control gate (22) only partially overlaps the floating gate (18); a semi-conducting layer (26) connected to the drain overlaps another part of the floating gate. It is this latter layer which establishes the considerable capacitive coupling according to the invention. Programming can then be carried out by Fowler Nordheim effect with the source at high impedance, that is to say with no hot-electron effect.
Bibliography:Application Number: EP19920403039