Integrated circuit fabrication process using a bilayer resist

A lithographic process for integrated circuit processing uses a two-level resist to reduce variations in nominally identical feature sizes as printed in the resist(e.g. 7) and as transferred into the substrate(e.g. 1), resulting from complex topography on the substrate surface.

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Bibliographic Details
Main Authors CUTHBERT, JOHN DAVID, FU, CHONGNG, OLASUPO, KOLAWOLE RAHMAN
Format Patent
LanguageEnglish
French
German
Published 03.02.1993
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A lithographic process for integrated circuit processing uses a two-level resist to reduce variations in nominally identical feature sizes as printed in the resist(e.g. 7) and as transferred into the substrate(e.g. 1), resulting from complex topography on the substrate surface.
Bibliography:Application Number: EP19920304598