Method of fabricating an integrated circuit

A semiconductor memory cell has parallel gates (e.g. 19,21,25,23). The direction of the gates (e.g. 19,21,25,23) is desirably chosen to minimize lithographic astigmatic effects. Thus gates of comparatively uniform width are produced and predictability of transistor performance thereby improved.

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Bibliographic Details
Main Authors LEE, KUO-HUA, SUNG, JANMYE, ADAMS, THOMAS EVANS, NAGY, WILLIAM JOHN
Format Patent
LanguageEnglish
French
German
Published 12.03.1997
Edition5
Subjects
ELECTRICITY
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Summary:A semiconductor memory cell has parallel gates (e.g. 19,21,25,23). The direction of the gates (e.g. 19,21,25,23) is desirably chosen to minimize lithographic astigmatic effects. Thus gates of comparatively uniform width are produced and predictability of transistor performance thereby improved.
Bibliography:Application Number: EP19920304177