A three wire half duplex asynchronous communication architecture
A controller and communications architecture for controlling the operation of computer I/O devices such as a keyboard or the like includes two microprocessors, a three-wire half duplex communications interface and a transmission protocol allow data transmission, error, detection and contention resol...
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Main Authors | , |
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Format | Patent |
Language | English French German |
Published |
16.09.1992
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Subjects | |
Online Access | Get full text |
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Summary: | A controller and communications architecture for controlling the operation of computer I/O devices such as a keyboard or the like includes two microprocessors, a three-wire half duplex communications interface and a transmission protocol allow data transmission, error, detection and contention resolution. The transmission protocol allows the microprocessors to transmit serial data over the interface which includes a single shared data line and two simplex clock lines. |
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Bibliography: | Application Number: EP19920480020 |