Phase lock loop

• Main Author: WINCN, JOHN M
• Format: Patent
• Language: English; French; German
• Published: 15.04.1992
• Subjects: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES; BASIC ELECTRONIC CIRCUITRY; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; PULSE TECHNIQUE; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

A complementary metal oxide semiconductor, single, phase-lock loop decoding apparatus allows extraction of a clock signal from Manchester-encoded data. A filter couples a phase-frequency detector to a voltage-controlled oscillator. Output of the voltage-controlled oscillator is fed back through a scaling circuit to the phase-frequency detector which is used to lock on to the reference signal. First, the reference signal is provided from an established reference frequency from a crystal-controlled oscillator having 0.01% resolution. A multiplexer selects the external clock reference in response to a select signal and directs the clock signal to the reference input of the phase-lock loop. The phase-lock loop is operated to lock onto the reference voltage. The phase-lock loop has a narrow bandwidth, fast acquisition time because of time constants established by the filter and the voltage-controlled oscillator. Upon receipt of a Manchester-encoded signal, the preamble portion of the signal is selected by use of the multiplexer and directed to the reference input of the detector. The phase-lock loop, in response to a control signal, suspends operation at a known transition until a corresponding transition in the preamble occurs. The phase-lock loop is started in a synchronized fashion with the reference signal and has a nominal frequency equal to that of the phase-lock loop. Therefore, the phase-lock loop is able to accurately track and lock onto the reference voltage within the few bit times of the preamble even though it has the narrow bandwidth. Thereafter, decoding data by use of an extracted clock, 5 MHz components of the data will not appreciably affect the operation of the phase-lock loop allowing accurate decoding of the signal. By completion of data, the multiplexer reselects the reference in anticipation of receipt of another data packet. The phase-frequency detector is sensitive to both phase and frequency and use of a charge pump in the detector allows operation of the phase-lock loop to be halted without appreciably affecting voltage levels into the voltage-controlled oscillator without adversely affecting any timing circuits such as one-shot timers used in the decoding circuit.