Signal routing in a stacked array of multiprocessor boards

A system is described for arraying multi-device processing nodes (1,2) in a 3-dimensional computing architecture and for flexibly connecting their ports. The topology of each processing node is of a fixed and constant physical geometry. The nodes may comprise a digital signal processor chip, a stati...

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Bibliographic Details
Main Authors SEGELKEN, JOHN MAURICE, WU, LESLEY JEN-YUAN, SHIVELY, RICHARD ROBERT, STANZIOLA, CHRISTOPHER ANTHONY
Format Patent
LanguageEnglish
French
German
Published 01.04.1992
Subjects
BASIC ELECTRIC ELEMENTS
CALCULATING
CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PHYSICS
PRINTED CIRCUITS
SEMICONDUCTOR DEVICES
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Summary:A system is described for arraying multi-device processing nodes (1,2) in a 3-dimensional computing architecture and for flexibly connecting their ports. The topology of each processing node is of a fixed and constant physical geometry. The nodes may comprise a digital signal processor chip, a static RAM, and a communications and network controller. The nodes or tiles are 4-connected, each having logical north, east, south and west ports. The nodes are mounted on boards (17,18,19). Selective connection of essentially any one port to another on a different board is effected by use of a routing and spacer element (50) having internal routing paths preselected to support a desired node interconnection architecture. Novel multiprocessing architectures and connections to a Host computer are also disclosed.
Bibliography:Application Number: EP19910306586